Many types of non-volatile storage arrays exist in the prior art that require specific voltages to write data into the array and that use very low currents and/or voltages to read data out of the array. As photolithographic geometries shrink, the smaller storage cells formed at each array storage location carry less current. As a result, the array read and write voltages and currents also decrease and must be controlled with increasing precision.
Furthermore, the reduction in geometries causes the resistance of conductors in the array—e.g., array row and column lines—to increase and to become non-negligible in relation to the read and write voltages and currents. Unlike larger-geometry arrays, in which the resistances and resultant voltage drops of row and column lines are insignificant compared to the supply voltages and may be ignored, the voltage drops on row and column lines in reduced-geometry arrays may be a significant percentage of the supply voltage. The combination of low read and write currents and/or voltages, along with higher line resistances, makes reading and writing to the array more difficult due to the increased internal array voltage drops.
For example, when writing a bit to the array, whether the storage element is a fuse, antifuse, phase change material, or other storage element, and particularly when the storage location is to hold more than one bit per cell, the voltage applied to the cell must typically fall within a precise tolerance. Depending on the distance traveled along a given row and a given column, however, the write voltage applied to a storage cell may vary. The write voltage applied to a storage cell that is located far from a write driver, for example, may be less than the write voltage applied to a closer storage cell; the lower voltage may be outside a tolerance limit, causing the write to fail. Likewise, when reading from the array by, for example, sensing a voltage on a cell, the sensed voltage may be modified by the resistance along the read path and resultant voltage drop, causing the read to fail due to inadequate voltage. In addition, the current through a storage cell may be affected by the voltage across the cell, which, in turn, may be detrimentally affected by the voltage drops along the read path. Clearly, a need exists for a memory array storage device that can cope with the reduced read and write voltages and increased row and column resistances associated with reduced photolithographic geometries.